Metal contamination is a major cause of deterioration in characteristics of a semiconductor device. For example, for a back-illuminated solid-state image sensing device, metal mixed into a semiconductor epitaxial wafer to be a substrate of the device causes increased dark current in the solid-state image sensing device, and results in formation of defects referred to as white spot defects. Recently, a back-illuminated image sensing device has been widely used for digital cameras and mobile phones such as smartphones because it can directly receive light from the outside, and take sharper images or motion pictures even in a dark place and the like due to the fact that a wiring layer and the like thereof are disposed at a lower layer than a sensor unit. Therefore, it is desirable to reduce white spot defects as much as possible.
Mixing of metal into a wafer mainly occurs in a process of producing a semiconductor epitaxial wafer and a process of producing a solid-state image sensing device (device fabrication process). Metal contamination in the former process of producing a semiconductor epitaxial wafer may be due to heavy metal particles from components of an epitaxial growth furnace, or heavy metal particles caused by metal corrosion of piping materials of the furnace due to chlorine-based gas used in epitaxial growth in the furnace. In recent years, such metal contaminations have been reduced to some extent by replacing components of epitaxial growth furnaces with highly corrosion resistant materials, but not to a sufficient extent. On the other hand, in the latter process of producing a solid-state image sensing device, heavy metal contamination of semiconductor substrates would occur in process steps such as ion implantation, diffusion, and oxidizing heat treatment in the producing process.
For these reasons, conventionally, heavy metal contamination of semiconductor epitaxial wafers has been avoided by forming, in the semiconductor wafer, a gettering sink for trapping the metal, or using a substrate, such as a high boron concentration substrate, having high ability to trap the metal (gettering capability).
In general, a gettering sink is formed in a semiconductor wafer by an intrinsic gettering (IG) method in which oxygen precipitates (commonly called a silicon oxide precipitate, and also called BMD: bulk micro defect) or dislocations that are crystal defects are formed within the semiconductor wafer, or an extrinsic gettering (EG) method in which the gettering sink is formed on the rear surface of the semiconductor wafer.
Here, a technique of forming gettering sites in a semiconductor wafer by ion implantation can be given as a technique for gettering heavy metal. JP 06-338507 A (PTL 1) discloses a producing method, by which carbon ions are implanted through a surface of a silicon wafer to form a carbon ion implanted region, and a silicon epitaxial layer is formed on its surface thereby obtaining a silicon epitaxial wafer. In that technique, the carbon ion implanted region functions as gettering sites.
Further, JP 2008-294245 A (PTL 2) discloses a method of forming a carbon implanted layer by implanting carbon ions into a silicon wafer, and then performing heat treatment using a rapid thermal annealing (RTA) apparatus for recovering the crystallinity of the wafer which has been disrupted by the ion implantation, thereby shortening the recovery heat treatment process.
Further, JP 2010-177233 A (PTL 3) discloses a method of producing an epitaxial wafer, comprising the steps of ion-implanting at least one of boron, carbon, aluminum, arsenic, and antimony at a dose in the range of 5×1014 atoms/cm2 to 1×1016 atoms/cm2 into a single crystal silicon ingot substrate; then cleaning the single crystal silicon ingot substrate subjected to the ion implantation, without recovery heat treatment; and then forming an epitaxial layer at a temperature of 1100° C. or more using a single wafer processing epitaxial apparatus.
In addition to such formation of a gettering sink, it is important to ensure high quality of a substrate per se of a semiconductor epitaxial wafer. In this respect, JP 11-147786 A (PTL 4) discloses a technique of producing a silicon single crystal wafer having extremely low defect density over the entire surface of the crystal by Czochralski process (CZ method).